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Espressif Systems /ESP32-S3 /EXTMEM /CORE0_ACS_CACHE_INT_ST

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Interpret as CORE0_ACS_CACHE_INT_ST

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CORE0_IBUS_ACS_MSK_ICACHE_ST)CORE0_IBUS_ACS_MSK_ICACHE_ST 0 (CORE0_IBUS_WR_ICACHE_ST)CORE0_IBUS_WR_ICACHE_ST 0 (CORE0_IBUS_REJECT_ST)CORE0_IBUS_REJECT_ST 0 (CORE0_DBUS_ACS_MSK_DCACHE_ST)CORE0_DBUS_ACS_MSK_DCACHE_ST 0 (CORE0_DBUS_REJECT_ST)CORE0_DBUS_REJECT_ST

Description

******* Description ***********

Fields

CORE0_IBUS_ACS_MSK_ICACHE_ST

The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access.
CORE0_IBUS_WR_ICACHE_ST

The bit is used to indicate interrupt by ibus trying to write icache
CORE0_IBUS_REJECT_ST

The bit is used to indicate interrupt by authentication fail.
CORE0_DBUS_ACS_MSK_DCACHE_ST

The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access.
CORE0_DBUS_REJECT_ST

The bit is used to indicate interrupt by authentication fail.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data